As a technology studied by the inventors of the present invention, for example, about a level conversion circuit, the following technology is considered.
FIG. 1 shows one example of input/output voltage waveforms of a level conversion circuit for conversion from a CML level to a CMOS level. In FIG. 1, the input of the level conversion circuit has a CML level (1.2V/0.9V) and the output has a CMOS level (1.2V/0V).
Application to a high-speed SerDes (Serializer Deserializer) requires a high-speed/low-power operation (5 GHz) and a Duty ratio compensation in addition to the level conversion function (1.2V/0.9V to 1.2V/0V). The Duty ratio herein means a value to quantitatively describe a distortion of pulse width, i.e., a ratio between a pulse width TW and a cycle time TC (Duty ratio=(TW/TC)·100%). Specifically, in a high-speed interface circuit premising a half-rate operation (a system of operating all circuits in sync referencing a rising time and a falling time of a clock pulse), a reference time of the operation depends on the Duty ratio. Thus, it is very important to keep the Duty ratio at 50%. Note that, in the study herein, based on a 90 nm CMOS device, a source voltage VDD is 1.2 V and Low/High levels of a signal are 0.9V/1.2V for CML level and 0V/1.2V for CMOS level.
Conventionally, such a level conversion circuit generally uses a differential circuit having a high gain as shown in FIG. 2. FIG. 2 is a circuit diagram showing a configuration of a conventional level conversion circuit.
Meanwhile, the applicants have done a prior art search based on the result of the invention. As a result, Japanese Patent Application Laid-Open Publication No. 59-099819 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 06-013878 (Patent Document 2) were extracted. Patent Document 1 discloses a level-shift circuit in FIG. 5 thereof and a generation circuit of reference voltage VCONT using the same level-shift circuit (replica) of FIG. 5 in FIG. 8. However, there is no description about a comparison circuit. And, Patent Document 2 discloses that “control is made . . . to match a first reference potential Vref1 which is outputted as a central potential of CMOS level and a second reference potential Vref2 which is outputted as a central potential of ECL level” in the Abstract. However, there is no description about a source follower circuit.